This application claims priority from Korean Patent Application No. 2001-52058, filed on Aug. 28, 2001, the contents of which are herein incorporated by this reference in their entirety.
The present invention is generally concerned with semiconductor memory devices and, more specifically, with nonvolatile semiconductor memory devices with the operation modes of erasing, programming, and reading, using a voltage higher than a power supply voltage.
Referring to FIG. 1, as a kind of nonvolatile semiconductor memory devices, a NOR-type flash memory includes a memory cell array 10, a row (X) decoder 20, a column gate circuit 30, a column (Y) decoder 40, and sense amplifiers/write drivers (SA/WD) block 50, in general.
The NOR-type memory cell array 10 comprises of plural memory cells coupled to wordlines WL and bitlines BL in a matrix pattern. Each memory cell, as shown in FIG. 2, is constructed of a stacked gate type for example, being made of source and drain regions formed in a P-type semiconductor substrate 2, 3 and 4, a floating gate 6 isolated from the source and drain regions through an oxide film 7 thinner than 100 xc3x85, and a control gate 8 formed over the floating gate 6 with an interlayer oxide film 9 interposed therebetween. The NOR-type flash memory has a multiplicity of bulk regions, isolated from each other, in which the memory cells are formed. Therefore, memory cells in the same bulk region are erased simultaneously in the unit of bulk, so referred to as a xe2x80x9csectorxe2x80x9d that for example covers the storage capacity of 64 Kb.
Returning to FIG. 1, a row decoder 20 selects one of wordlines WL1xcx9cWLi in response to a row address, and a column gate circuit 30 selects a part of bitlines BL1xcx9cBLj in response to column selection signals Y1xcx9cYn provided from a column decoder 40. The selected bitlines are connected to the SA/WD block 50. The column gate circuit 30 is constructed of high-voltage specific NMOS transistors, T11xcx9cTn1, T12xcx9cTn2, . . . , T1mxcx9cTnm, which are connected to the bitlines BL1xcx9cBLj each of which corresponds to a group of the n-numbered transistors. The SA/WD block 50 senses data from a selected memory cell through its corresponding bitline during a read operation while it drives data into a selected memory cell during a program operation.
The following Table 1 shows voltage biasing states for performing relevant operations in the NOR-type flash memory.
Programming a memory cell involves hot electron injection by which a ground voltage (i.e., 0V) is applied to the source and substrate, a high voltage (e.g., +10V) to the control gate, and an appropriate positive voltage (e.g., +5xcx9c6V) to the drain region. The high positive voltage Vg, applied to control gates of memory cell transistors, is supplied from the row decoder 20. The positive voltage to the drain region, Vd, is supplied from the write driver 50 through the column gate circuit 30 in which a positive voltage of +5Vxcx9c+6V is applied to gates of the selected NMOS transistors among T11xcx9cTnm. With the voltage biases, electrons (or negative charges) accumulate in the floating gate, resulting in an elevation of the transistor""s threshold voltage. A programmed memory cell has a threshold voltage of +6Vxcx9c+7V, being detected as an xe2x80x9coff-cellxe2x80x9d when read.
Erasing the memory cells involves the Fowler-Nordheim (F-N) tunneling effect. A high (-potential) negative voltage of about xe2x88x9210V is applied to gates of memory cells while an appropriate positive voltage of about +5V biases the substrate (or bulk) of the memory cells. The drain region of the memory cell is in a floating state (or a high-impedance state) in order to maximize an erasing effect. The high negative voltage applied to the control gate of the memory cell is supplied from the row decoder 20. Under the condition of voltage-biasing to erase the memory cells, a strong electric field of 6xcx9c7 MV/cm over the oxide film 7 between the floating gate 6 and the substrate 2 induces the F-N tunneling, thus reducing a threshold voltage of the memory cell. The erased memory cell is detected as an xe2x80x9con-cellxe2x80x9d.
Reading a memory cell to distinguish a current state of the memory cell is achieved by applying an appropriate positive voltage of about +1V to the drain region 4, applying a positive voltage of about +4.5V to the control gate through a selected wordline, and applying 0V to the source region. The drain voltage (Vd) is supplied from the sense amplifier of the SA/WD block 50 through the column gate circuit 30, and the gate voltage (Vg) is supplied from the row decoder 20. If a selected memory cell has been programmed, there is no current flow through the programmed memory cell because its threshold voltage was set higher. Therefore, a voltage on a corresponding bitline increases and the sense amplifier detects the memory cell as an off-cell. On the other hand, if a selected memory cell has been erased, a current flows from the source region to the drain region, and a decreased voltage on a corresponding bitline lets the sense amplifier detect the memory cell as an on-cell.
As a high voltage beyond 5V is applied to the drain region during the program operation, the column gate circuit 30 employs high-voltage specified NMOS transistors (hereinafter, referred to as xe2x80x9cHVNMOS transistorsxe2x80x9d) T11xcx9cTnm in order to transfer the high voltage to the memory cells in full rate. Such a HVNMOS transistor is operative at a higher voltage than a power supply voltage, with a thick gate oxide film by which its threshold voltage is about +3V higher than a normal NMOS transistor having a threshold voltage of +0.5xcx9c+0.7V.
During a read operation, the voltage level around the power supply voltage, e.g., 3xcx9c5V, is established on a gate of the HVNMOS transistor in order to transfer the drain voltage of 1V to the drain region of the selected memory cell. However, if the power supply voltage becomes lower, the current drivability of the HVNMOS transistor degrades and accordingly the reading speed decreases. As a result, high-speed operation of the NOR flash memory device is impeded.
Embodiments of the present invention provide a nonvolatile memory device maintaining higher reading speed for memory cells which using a lower power supply voltage.
Features and advantages of embodiments the invention will be more fully described by reference to the accompanying drawings.